The AAD08S050G is a high‑speed analog‑to‑digital converter fabricated with CMOS process. It delivers a maximum sampling rate of 50 GS/s with 8‑bit resolution, enabling direct sampling of signals ranging from DC to 20 GHz. Adopting a time‑interleaved architecture, the chip integrates 128 sub‑range SAR ADCs. For output interfaces, it is equipped with 16 high‑speed serial output ports, each supporting a rate up to 25 Gbps. The device is packaged in an advanced BGA225 form factor.

This chip features three major technological innovations:

First, in the design of the sampler front‑end, it achieves breakthroughs in ultra‑wideband analog front‑ends, on‑chip transmission lines, and low‑jitter sampling clock retiming technologies, addressing the challenges of ultra‑wideband and high‑linearity sampling for ADCs.

Second, in time calibration technology, a hybrid digital‑analog calibration scheme is adopted to greatly suppress interleaving errors. For nonlinear errors, foreground calibration is deployed to further improve linearity performance.

Third, in high‑precision synchronization mechanisms, a hierarchical retiming synchronization architecture is proposed. It overcomes technical bottlenecks including reset timing positioning, conversion time phasing and data transmission alignment, realizing picosecond‑level precise synchronization from data conversion to remote data reception.

As China’s sole mass‑produced ultra‑high‑speed ADC with a sampling rate of 50 Gsps, this product reaches world‑leading technological levels. It is widely applicable to high‑end oscilloscopes, broadband communication systems, high‑speed data acquisition systems and other scenarios.

Moving forward, Acela Micro will continue to deepen technological research, expand market coverage, accelerate the localization of high‑performance analog signal chain chips in China, and strive to become a leader in the domestic analog semiconductor industry.